Hardware Trojan horses (HTH) have recently emerged as a major security threat for field-programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs show that a considerable amount of logic resources are left unused to be misused by malicious attacks. A low-level protection and detection scheme for FPGAs is proposed by filling the unused resources with dummy logic. The unused resources at the device layout-level are identified and replaced by dummy logic cells for different resources. An intrusion detection system is used to detect the presence of Trojans using pattern matching techniques. The proposed HTH detection and protection scheme has been applied on Xilinx Virtex devices implementing a set of IWLS benchmarks. The results show that the chance of logic abuse can be significantly reduced by employing the proposed HTH detection and protection scheme. Experimental results also show that as compared to unprotected designs, the proposed HTH scheme imposes no performance and power penalties.